Challenges in sub-0.13 μm front-end-of-line processes

Author

Zheng, Jia-Zhen ; Hsia, Liang-Choo

Author_Institution

Technol. Dept., Chartered Semicond. Manuf. Ltd, Singapore, Singapore

Volume

1

fYear

2001

fDate

2001

Firstpage

52

Abstract

The scaling of CMOS devices to 0.13 μm and beyond involves major process adjustments on all fronts. In this paper, we outline device requirement and processing challenges in the front-end-of-line (FEOL) processes down to 0.07 μm technology node. We explore the most critical challenges in lithography, isolation, gate dielectrics, transistor implants and salicide, and show that process solutions exist for 0.1 μm technology node with more research work needed for 0.07 μm technology node

Keywords

CMOS integrated circuits; etching; integrated circuit metallisation; integrated circuit technology; isolation technology; lithography; 0.07 to 0.13 micron; CMOS device scaling; FEOL processes; front-end-of-line processes; gate dielectric scaling; isolation; lithography; shallow trench isolation; silicide engineering; transistor implants; CMOS technology; Dielectrics; Etching; Integrated circuit technology; Isolation technology; Lithography; Manufacturing processes; Process control; Production; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981423

Filename

981423