A 0.11 μm DRAM technology for 4Gb DRAM and beyond

Author

Kim, Kinam ; Park, Joo-Sung

Author_Institution

Memory Device Bus., Samsung Electron. Co., Kyungki, South Korea

Volume

1

fYear

2001

fDate

2001

Firstpage

178

Abstract

A 1.8 V 650 mm² 4Gb DRAM fabricated with 0.10 μm² cell size has been successfully developed using 0.11 μm DRAM technology. Well-proven KrF lithography has been extended with various resolution enhancement techniques for 0.11 μm DRAM technology. 80 nm array transistor and sub-80 nm memory cell contact, which are the smallest array transistor ever reported, are successfully developed for high functional yield as well as high chip performance. In addition, many novel DRAM technologies are developed and will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node selfaligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal interconnections

Keywords

DRAM chips; electrical contacts; integrated circuit interconnections; photolithography; 0.11 micron; 1.8 V; 4 Gbit; 80 nm; CVD Al process; DRAM integration; DRAM technology; KrF lithography; MIS capacitor; W-bit line; array transistor; borderless metal contact; high chip performance; high functional yield; line-type storage node selfaligned contact; mechanically stable metal-insulator-silicon capacitor; memory cell contact; metal interconnections; oxide gap-filling; resolution enhancement techniques; stud contact; Annealing; Chemical technology; Cleaning; Contact resistance; Hydrogen; Polymers; Random access memory; Scalability; Silicon compounds; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981451

Filename

981451