Diagnosis of path delay faults

Author

Sivaraman, Mukund ; Strojwas, Andrzej J.

Author_Institution

Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

2

fYear

1995

fDate

13-16 Aug 1995

Firstpage

769

Abstract

We introduce the problem of diagnosing path delay faults in chips which, after fabrication, fail to exhibit correct timing behavior for a set of tests. If a fabricated chip fails for a set of delay fault tests, we locate the paths which are likely to have caused the failure. A sensitization approach based on signal stabilizing times, followed by a probability analysis under the assumption of independently varying gate and interconnect delays is presented here as a solution to this problem. Further extensions to correlated delay models are also proposed

Keywords

delays; fault diagnosis; integrated circuit interconnections; integrated circuit testing; logic testing; probability; production testing; timing; correlated delay models; fault diagnosis; gate delays; interconnect delays; logic testing; path delay faults; probability analysis; sensitization approach; signal stabilizing times; timing behavior; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fabrication; Fault diagnosis; Integrated circuit interconnections; Propagation delay; Signal analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-7803-2972-4

Type

conf

DOI

10.1109/MWSCAS.1995.510202

Filename

510202