DocumentCode
2206181
Title
Gate size optimization for row-based layouts
Author
Maheshwari, Naresh ; Sapatnekar, Sachin S.
Author_Institution
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume
2
fYear
1995
fDate
13-16 Aug 1995
Firstpage
777
Abstract
A transistor sizing algorithm for row-based layouts is presented under an improved area model. This algorithm uses convex programming to find a minimal area circuit for a given delay specification. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuits indicate a significant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer
Keywords
CMOS logic circuits; circuit layout CAD; circuit optimisation; convex programming; delays; logic CAD; CMOS circuits; area model; convex programming; delay specification; gate size optimization; minimal area circuit; minimum delay; row heights; row-based layouts; transistor sizing algorithm; Aerospace industry; Area measurement; Clocks; Constraint optimization; Delay; Design optimization; Macrocell networks; Registers; Routing; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location
Rio de Janeiro
Print_ISBN
0-7803-2972-4
Type
conf
DOI
10.1109/MWSCAS.1995.510204
Filename
510204
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