Novel sub-25 nm devices [MOSFETs]

Recently, there has been much discussion concerning the scaling of MOSFETs into sub-50 nm dimensions. Many fundamental device problems such as short channel effects (DIBL and V_th roll-off), off-state, leakage current, parasitic capacitance and resistance, and gate tunneling current are currently being examined. It is apparent that sub-50 nm transistors can be realized with performance limited primarily by parasitics such as series resistance and capacitance. However, for sub-50 nm devices, new innovation is necessary. The difficulties and challenges to further scaling of CMOS, from digital as well as analog viewpoint are discussed in this paper. Possible new solutions like single pocket structures, Schottky MOSFETs, and double gate MOSFETs are also discussed in this context