Plasma process-induced charging during PECVD overlay nitride deposition

Author

Moens, P. ; Viaene, J. ; Dobbelaere, W. ; Jastrzebski, L.

Author_Institution

Alcatel Mietec, Oudenaarde, Belgium

fYear

1998

fDate

4-5 Jun 1998

Firstpage

68

Lastpage

71

Abstract

Gate oxide degradation can occur during PECVD of the overlay nitride layer. In this paper, plasma damage monitor (PDM) and surface charge imaging (SCI) techniques are used to detect plasma damage on a Novellus Concept One PECVD system. By comparing the data with electrical transistor parameter shifts, the most important charging sources could be identified

Keywords

dielectric thin films; integrated circuit reliability; integrated circuit testing; integrated circuit yield; plasma CVD; silicon compounds; surface charging; Novellus Concept One PECVD system; PECVD; PECVD overlay nitride deposition; Si; Si₃N₄-SiO₂-Si; charging sources; electrical transistor parameter shifts; gate oxide degradation; overlay nitride layer; plasma damage; plasma damage monitor technique; plasma process-induced charging; surface charge imaging technique; CMOS process; Ceramics; Conductivity; Current measurement; Frequency; Furnaces; Monitoring; Oxidation; Plasma measurements; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1998 3rd International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

0-9651577-2-5

Type

conf

DOI

10.1109/PPID.1998.725576

Filename

725576