Charging damage evaluation in 0.25~0.3 μm polycide gate etching processes

Charging damage evaluation of 0.25-0.3 μm polycide gate etching processes in four commercial polycide etch process systems for 200 mm wafers is performed with time-to-breakdown (T_bd), charge-to-breakdown (Q_bd), and initial-electron-trapping-rate (IETR, dV/dt) measurements using metal-oxide-semiconductor (MOS) capacitors and with flatband-voltage-shift (ΔV_fb) measurement of metal-nitride-oxide-semiconductor (MNOS) capacitor test structures. All gate etching processes are optimized for 0.25~0.3 μm polycide gate patterning and are found to have minimal plasma damage. The sensitivity and limitations of these measurement methods are demonstrated in the evaluation of the charging characteristics of these gate etching processes