A Novel 3D Embedded Gate Field Effect Transistor: Device Concept and Modelling

Author

Fobelets, K. ; Ding, P.W. ; Velazquez-Perez, J.E.

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. London

fYear

0

fDate

0-0 0

Firstpage

455

Lastpage

458

Abstract

A novel 3D Field Effect Transistor on SOI - the screen grid FET (SGFET) $for ultra-low power applications is proposed and TCAD analysis of the device is presented. The device is designed with the aim of decoupling the need for aggressive scaling of the gate oxide thickness when reducing the channel length. Other scaling objectives are: retaining low doping in the channel, maintaining the drain conductance and optimizing the low power/low voltage device behaviour. The simulation results show that these objectives are fulfilled: oxide thickness and channel doping have a reduced influence on the threshold voltage and do not need to be scaled aggressively to reduce the short channel effects. Finally, we show that the device performance for low-power/low-voltage applications is excellent

Keywords

embedded systems; field effect transistors; silicon-on-insulator; technology CAD (electronics); 3D embedded gate field effect transistor; SGFET; SOI; TCAD analysis; aggressive scaling; channel doping; channel length reduction; drain conductance; gate oxide thickness; low power/low voltage device behaviour; short channel effects; ultra-low power applications; Circuits and systems; Electronics industry; Energy consumption; Engine cylinders; FETs; Leakage current; Low voltage; Semiconductor device doping; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2006 25th International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0117-8

Type

conf

DOI

10.1109/ICMEL.2006.1650999

Filename

1650999