Investigation of the Novel Attributes of a Vertical MOSFET with Internal Block Layer (bVMOS): 2-D Simulation Study

In this paper, a vertical n-channel enhancement-type MOSFET with internal block layer (bVMOS) is investigated theoretically. In the proposed structure, the internal block layer comprises a buried block layer and a sidewall block layer. We also test three blocking materials (ex. doped Si, nitride and oxide) for performance comparisons. That is, the p-n junction region between the substrate and drain is isolated by the buried block layer thereby reducing the p-n junction leakage current and the parasitic capacitance. Similarly, the electrical field between the body and drain is blocked or shielded by the sidewall block layer; hence the intolerable ultra-short-channel effects, such as drain-induced barrier lowering (DIBL), hot-carrier effect, source/drain (S/D) punchthrough, and charge-sharing effect, are ameliorated tellingly. Owing to the suppression of the ultra-short-channel effects, excellent subthreshold swing is also successfully achieved by the nano-scale regime. Moreover, the proposed vertical structure has a path between the body and the substrate, the generated hole current by impact ionization and generated heat in channel can be banished from this pass way. Thus, both the floating-body effects and the self-heating effects are avoided synchronously