DocumentCode
2207832
Title
MOS scaling crisis and SOI technology
Author
Yoshimi, Makoto
Author_Institution
Syst. LSI Res. & Dev. Center, Toshiba Corp., Yokohama, Japan
Volume
1
fYear
2001
fDate
2001
Firstpage
637
Abstract
The current status of SOI technology is reviewed and its future directions are discussed. It is shown that unique features in device characteristics as well as process flexibility will provide SOI technology with the possibility of circumventing the crisis and creating a new field which is not realized by bulk Si MOSFETs
Keywords
CMOS integrated circuits; DRAM chips; silicon-on-insulator; CMOS structure; DRAM; SOI technology; device characteristics; process flexibility; scaling; Acceleration; CMOS technology; Circuits; Costs; High K dielectric materials; Large scale integration; Low-noise amplifiers; MOSFETs; Moore´s Law; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6520-8
Type
conf
DOI
10.1109/ICSICT.2001.981561
Filename
981561
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