An efficient multidimensional/multidirectional parallel pipelined architecture for image processing

The architecture of a multidimensional and multidirectional parallel pipeline system is presented. It is based on the concept of algorithm-to-architecture mapping whereby different stages of the pipeline can be dynamically reconfigured to suit different task divisions in terms of processing power or memory required. The system has a high degree of fault tolerance provided by the multiple interconnection links among the processing elements within each stage and between different stages. An 8-PEs prototype version of the system has been built and tested under various configurations of pipeline stages. A combination of various algorithms have been implemented on the system and predicted results are obtained