Using Spice and behavioral synthesis tools to optimize ASICs´ peak power consumption

This paper describes a methodology that combines Spice simulations with a behavioral synthesis tool to estimate and optimize digital ASICs´ peak power consumption. Spice can be used to provide very accurate and complete measures of power consumption. A behavioral-level tool is then used to minimize the use of power in each clock cycle by carefully selecting the appropriate hardware, while simultaneously scheduling operations. Results show substantial reductions in peak power