Neural network based optimization of CMOS transistor sizing for leakage power minimization

Reduction of power dissipation makes an electronic device more efficient and reliable. The need for a device that dissipates less power was the motivation for the development of CMOS technology. In this paper, a novel technique for optimizing electronic circuits by resizing transistor parameters using single perceptron neural network is proposed. Simulation results have shown that the neural network based approach used in transistor resizing exhibits better simplicity, better optimization of complex circuits and less computational requirements. The average improvement of leakage power reduction is about 32% for C17 circuit which was simulated assuming 22 nanometer technology.