A 0.18 /spl mu/m dual-gate CMOS model for the design of 2.4 GHz low noise amplifier

Author

Liang, Kung-Hao ; Chan, Yi-Jen

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chungli

fYear

2006

fDate

11-13 June 2006

Abstract

A dual-gate TSMC 0.18 mum gate-length n-MOS has been measured and characterized. The modified dual-gate large-signal model consists of two intrinsic, single-gate conventional BSIM3v3 nonlinear models and the passive network is proposed representing the device parasitic effects. This large-signal rf model includes the required passive components to fit the device dc and rf characteristics. The extrinsic elements of capacitance and inductance are calculated from the three-port S-parameters. Good agreement has been obtained between the simulation results of the equivalent circuit model and the measured data up to 15 GHz. In order to verify this modified model, a 2.4 GHz dual-gate low noise amplifier was designed based on this modified model. The LNA measurement results are consistent with the simulations, which demonstrate that the cascode-type dual-gate CMOS model can be applied for microwave circuit design

Keywords

CMOS integrated circuits; UHF amplifiers; equivalent circuits; integrated circuit design; integrated circuit modelling; low noise amplifiers; passive networks; 0.18 micron; 2.4 GHz; BSIM3v3 nonlinear models; device parasitic effects; dual-gate CMOS model; dual-gate large-signal model; equivalent circuit model; low noise amplifier; microwave circuit design; passive network; three-port S-parameters; Circuit noise; Circuit simulation; Equivalent circuits; Inductance; Low-noise amplifiers; Parasitic capacitance; Passive networks; Radiofrequency amplifiers; Scattering parameters; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-9572-7

Type

conf

DOI

10.1109/RFIC.2006.1651154

Filename

1651154