Verification of RF SoCs: RF, analog, baseband and software

Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of such complex ICs that accept input close to the RF carrier frequency and are analyzed for receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors in deep-submicron technologies