Producing secure pseudorandom sequences with combined multiplicative congruential generators

In this paper, we propose a novel method for producing secure pseudorandom sequences with combined multiplicative congruential generators that have been defined recently. The specific properties of field programmable gate arrays (FPGA) and the combined multiplicative congruential generators enable the generation of secure sequences in only three cycles of the system clock. The output bit rate of the described design, which is composed of eight generators, achieves 1.227 Gbit/s, and this rate can be significantly increased with more generators. In practice the output throughput is limited only by the available resources of the FPGA used in the design.