Serial LDPC decoding on a SIMD DSP using horizontal scheduling

Author

Gomes, Marco ; Silva, Vitor ; Neves, Claudio ; Marques, Ricardo

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Coimbra, Coimbra, Portugal

fYear

2006

fDate

4-8 Sept. 2006

Firstpage

1

Lastpage

5

Abstract

In this paper we propose an efficient vectorized low density parity check (LDPC) decoding scheme based on the min-sum algorithm and the horizontal scheduling method. Also, the well known forward-backward algorithm, used in the check-node messages update, is improved. Results are presented for 32 and 16 bits logarithm likelihood ratio messages representation on a high performance and modern fixed point DSP. The single instruction multiple data (SIMD) feature was explored in the 16 bits case. Both regular and irregular codes are considered.

Keywords

digital signal processing chips; parallel machines; parity check codes; processor scheduling; vectors; 16 bits logarithm likelihood ratio messages representation; 32 bits logarithm likelihood ratio messages representation; SIMD DSP; check-node messages update; fixed point DSP; fixed point digital signal processor; forward-backward algorithm; horizontal scheduling method; irregular codes; min-sum algorithm; regular codes; serial LDPC decoding; single instruction multiple data; vectorized low density parity check decoding scheme; Abstracts; Bismuth; Decoding; Integrated circuits; Manganese;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2006 14th European

Conference_Location

Florence

ISSN

2219-5491

Type

conf

Filename

7071043