Multilevel dual-channel NAND flash memories with high-speed read and verifying program

Author

Kim, Jae-Ho ; Lee, Joung-Woo ; Kyung-Sik ; Whan Kim, Tae

Author_Institution

Adv. Semicond. Res. Center, Hanyang Univ., Seoul

Volume

1

fYear

2006

fDate

22-25 Oct. 2006

Firstpage

382

Lastpage

383

Abstract

The multilevel dual channel (MLDC) NAND flash memory cell structures with asymmetrically-doped channel regions are proposed. The channel structures with a MLDC flash cell consisted of the two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell provided the high-speed multilevel reading and program verifying due to the sensing of the discrete current levels utilizing the unique asymmetric channel structure.

Keywords

NAND circuits; circuit CAD; circuit simulation; flash memories; program verification; semiconductor doping; asymmetric channel structure; computer aided design simulation; doping channel; high-speed read program; multilevel dual-channel NAND flash memories; program verifying; Computational modeling; Computer simulation; Doping; Multi-Level Dual-Channel; asymmetrically-doped channel; current sensing; reduce reading and program verifying time;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE

Conference_Location

Gyeongju

Print_ISBN

978-1-4244-0540-4

Electronic_ISBN

978-1-4244-0541-1

Type

conf

DOI

10.1109/NMDC.2006.4388777

Filename

4388777