Integration of vertical pnp transistors in a double-polysilicon Bi-CMOS process

Author

de Lang, D. ; Bladt, E. ; Goor, A. V D ; Josquin, W.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1989

fDate

18-19 Sep 1989

Firstpage

190

Lastpage

193

Abstract

A cost-effective method for integrating vertical pnp transistors in an advanced double-poly BiCMOS process is discussed. The method requires only two additional masks for modification of the buried layer structure. Vertical pnp transistors with an f_t of 1 GHz have been realized in combination with 7-GHz npn transistors. 2-D simulations of the buried layer process shows a greatly improved isolation and a large reduction in substrate capacitance. Both the AC and DC characteristics of the vertical pnp transistor are adequate for a wide range of analog applications

Keywords

BIMOS integrated circuits; bipolar transistors; integrated circuit technology; linear integrated circuits; 1 GHz; 2-D simulations; 7 GHz; AC characteristics; BiCMOS; DC characteristics; buried layer process; double-polysilicon Bi-CMOS process; improved isolation; polycrystalline Si; reduction in substrate capacitance; two additional masks; vertical pnp transistor integration; Analog circuits; Boron; Capacitance; Circuit simulation; Doping profiles; Filters; Isolation technology; Laboratories; Substrates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1989.69489

Filename

69489