3-D memory organization and performance analysis for multi-processor network-on-chip architecture

Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the hard disk drives (HDD). Recent trends show that the solid state drives (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.