A single chip HDD PRML channel

Author

Ahn, T.W. ; Chen, G. ; Hua, B. ; Kim, C.J. ; Knee, D. ; Kondo, A. ; Kuo, B. ; Lan, I.J. ; Ng, M. ; Shen, F. ; Yeh, N.H. ; Young, J.K.

Author_Institution

Samsung Semicond., San Jose, CA, USA

fYear

1996

fDate

5-8 May 1996

Firstpage

285

Lastpage

288

Abstract

A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 μm BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/sec. Under normal operating conditions the power dissipation is less than 800 mW. The on-chip circuitry includes ADC, VGA, FIR filter, Viterbi decoder, two PLL´s, etc

Keywords

BiCMOS integrated circuits; Viterbi decoding; hard discs; maximum likelihood detection; mixed analogue-digital integrated circuits; partial response channels; 0.8 micron; 120 Mbit/s; 800 mW; PRML channel chip; hard disk drive; mixed-signal BiCMOS process; onchip ADC; onchip FIR filter; onchip PLL; onchip VGA; onchip Viterbi decoder; partial response maximum likelihood channel; read functions; servo functions; single chip HDD PRML channel; write functions; BiCMOS integrated circuits; Cutoff frequency; Delay lines; Finite impulse response filter; Gain control; Hard disks; Magnetic recording; Maximum likelihood decoding; Maximum likelihood detection; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510560

Filename

510560