• DocumentCode
    2215485
  • Title

    FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks

  • Author

    Ferreira, Ricardo ; Vendramini, Julio C Goldner

  • Author_Institution
    Dept. de Inf., Univ. Fed. de Vicosa - UFV, Vicosa, Brazil
  • fYear
    2010
  • fDate
    Aug. 31 2010-Sept. 2 2010
  • Firstpage
    550
  • Lastpage
    555
  • Abstract
    Due to the large amount of experimental data provided by DNA microarrays, different kinds of computational methods have been proposed to study gene interactions. These methods are computationally very intensive. More specifically, this work focuses on an efficient approach to compute the attractor cycles in gene regulatory networks, which are modeled by Boolean graphs. This work proposes to explore the inherent parallelism of this approach by using a FPGA based implementation. In addition, we also propose a runtime framework to dynamically insert/delete edges at low cost by using a multistage interconnection network (MIN). We also show that MIN could be efficiently mapped on FPGAs by taking advantages of embedded memory modules. The MIN implementation is close to theoretical complexity O(n lg n). Moreover, we propose a heterogeneous node set, where few nodes are strongly connected and most nodes are poorly connected, which allow us to handle efficiently scale free topologies. Furthermore, our approach is synthesized once onto a FPGA and several simulations are performed, without the need of re-synthesis. Experimental results have shown acceleration gains up to three orders of magnitude compared to sequential approaches.
  • Keywords
    Boolean algebra; complex networks; computational complexity; embedded systems; field programmable gate arrays; genetics; graph theory; lab-on-a-chip; multistage interconnection networks; DNA microarray; FPGA; attractor computation; boolean graph; embedded memory; multistage interconnection network; scale free gene regulatory network; theoretical complexity; FPGA; Gene Regulatory Networks; Multistage Interconnection Networks; Scale Free;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2010 International Conference on
  • Conference_Location
    Milano
  • ISSN
    1946-1488
  • Print_ISBN
    978-1-4244-7842-2
  • Type

    conf

  • DOI
    10.1109/FPL.2010.108
  • Filename
    5694309