Delay analysis for BiCMOS drivers

Author

Rosseel, G.P. ; Dutton, R.W. ; Mayaram, K. ; Pederson, D.O.

Author_Institution

Stanford Univ., CA, USA

fYear

1988

fDate

12-13 Sep 1988

Firstpage

220

Lastpage

222

Abstract

Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated

Keywords

BIMOS integrated circuits; bipolar transistors; circuit analysis computing; delays; driver circuits; semiconductor device models; BiCMOS drivers; CODECS; SPICE simulations; bipolar transistors; circuit parameters; collector doping concentrations; delay models; device simulator; epi-layer thickness; gate delay; high-level injection effects; BiCMOS integrated circuits; Bipolar transistors; Circuit simulation; Codecs; Delay; Doping; Driver circuits; Equations; SPICE; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51083

Filename

51083