An asynchronous totally self-checking two-rail code error indicator

Author

Gaitanis, Nikolaos ; Gizopoulos, Dirnitris ; Paschalis, Antonis ; Kostarakis, Panagiotis

Author_Institution

Inst. of Inf., NCSR "Demokritos", Athens, Greece

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

151

Lastpage

156

Abstract

In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors´ knowledge, is the only existing TSC error indicator in the open literature

Keywords

CMOS logic circuits; VLSI; asynchronous circuits; automatic testing; delays; error detection; integrated circuit testing; logic testing; CMOS implementation; asynchronous TSC error indicator; concurrent detection; delay faults; totally self-checking error indicator; two-rail code error indicator; Circuit faults; Circuit testing; Computer errors; Delay effects; Electrical fault detection; Error-free operation; Fault detection; Military computing; Monitoring; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510850

Filename

510850