• DocumentCode
    2219765
  • Title

    Power efficient data cache designs

  • Author

    Abella, Jaume ; González, Antonio

  • Author_Institution
    Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
  • fYear
    2003
  • fDate
    13-15 Oct. 2003
  • Firstpage
    8
  • Lastpage
    13
  • Abstract
    We investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multibanked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.
  • Keywords
    CMOS digital integrated circuits; cache storage; power consumption; cache architecture; cache bank; cache organization; data cache design; energy consumption; multibanked organization; threshold voltage; Capacitance; Circuits; Computer architecture; Energy consumption; Low voltage; Power dissipation; Power system modeling; Process design; Signal processing; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2003. Proceedings. 21st International Conference on
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-2025-1
  • Type

    conf

  • DOI
    10.1109/ICCD.2003.1240866
  • Filename
    1240866