• DocumentCode
    2220568
  • Title

    Pipelined multiplicative division with IEEE rounding

  • Author

    Even, Guy ; Seidel, Peter-M

  • Author_Institution
    Dept. of Electr. Eng., Tel Aviv Univ., Israel
  • fYear
    2003
  • fDate
    13-15 Oct. 2003
  • Firstpage
    240
  • Lastpage
    245
  • Abstract
    We propose optimized pipelined implementations for Goldschmidt´s division algorithm with IEEE rounding based on Booth radix-8 multiplication. Compared to other FP-division algorithms, our implementations require fewer clock cycles and admit shorter clock periods. The considered optimizations for the quotient approximation are based on a careful general analysis of tight error bounds for the implementation and are accompanied by the utilization of redundant representations, partial compressions, injection-based rounding, and rectangular multipliers for the internal computations. To efficiently achieve IEEE compliant rounding, we introduce the concept of dew-point rounding that allows efficient implementation and reduced requirements for the quotient approximation. On this basis, we propose the implementation of different versions of Goldschmidt´s division algorithm with different pipeline depths. None of these implementations requires a full-sized multiplier at any stage of the computations. In this way we reduce latency, cost, and enable increased throughput at a reasonable cost. We suggest a full range of pipelining depths: On one extreme is a 3-stage pipeline with a restart time that simply equals the latency minus the number of pipeline stages. On the other extreme is a fully pipelined design.
  • Keywords
    floating point arithmetic; microprocessor chips; multiplying circuits; pipeline arithmetic; roundoff errors; 3-stage pipeline; Booth radix-8 multiplication; Goldschmidt´s division algorithm; IEEE rounding; dew-point rounding; full-sized multiplier; injection-based rounding; partial compression; quotient approximation; rectangular multipliers; redundant representation; Circuits; Clocks; Computer science; Costs; Delay; Error analysis; Hardware; Microprocessors; Pipeline processing; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2003. Proceedings. 21st International Conference on
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-2025-1
  • Type

    conf

  • DOI
    10.1109/ICCD.2003.1240901
  • Filename
    1240901