A silicon efficient FLEX 6000 programmable logic architecture

Author

Sung, Chiakang ; Cliff, Richard ; Huang, Joseph ; Wang, Xaobao ; Nguyen, Khai ; Xiaobao Wang ; Veenstra, Kerry ; Pedersen, Bruce ; Turner, John

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

273

Lastpage

276

Abstract

An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routing and high cost efficiency in the interconnect, logic array blocks, and I/O elements. Other architecture features include built-in low skew clock, programmable output slew rate control, PCI compliant I/O, JTAG boundary scan, individual output enable for each I/O pin, and in-circuit configuration. The first member of the family is currently available with 16000 gate density and 125 MHz performance for 16-bit counter application

Keywords

CMOS logic circuits; integrated circuit interconnections; integrated circuit layout; logic design; network routing; programmable logic arrays; 125 MHz; FLEX 6000 PLD architecture; I/O elements; JTAG boundary scan; PCI compliant I/O; SRAM based PLD architecture; built-in low skew clock; flexible routing; incircuit configuration; interconnect scheme; logic array blocks; programmable output slew rate control; routability; silicon efficient logic architecture; triple layer CMOS process; Clocks; Costs; Integrated circuit interconnections; Logic arrays; Logic devices; Programmable logic arrays; Programmable logic devices; Routing; Silicon; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694979

Filename

694979