A VLSI implementation of a low complexity Reed-Solomon encoder and decoder for CDPD

Author

Qun, Ge ; Junfa, Mao ; Mengtian, Rong

Author_Institution

Dept. of Electron. Eng., Shanghai Jiao Tong Univ., China

fYear

2001

fDate

2001

Firstpage

435

Lastpage

439

Abstract

This paper presents VLSI implementation of an area efficient 8-error correcting (63,47) Reed-Solomon(RS) encoder and decoder for the CDPD (cellular digital packet data)communication systems. We implement this RS decoder using Euclidean algorithms which are regular, simple and naturally suitable for VLSI implementation. Constant multipliers based on certain composite fields are deployed in the encoder, which significantly decreases the encoder´s area. Multipliers over a certain composite field GF((2)2) adopted in this paper lower the complexity of the multiplication of the decoder. The RS encoder and decoder can independently operate at a clock frequency of 30 MHz. This chip was fabricated in 0.6μm CMOS 1P2M technology with a supply of voltage of 5V, with die area 4mm × 4mm. The chip has been fully tested and stratifies the demand of the CDPD communication systems

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; cellular radio; codecs; decoding; digital radio; packet radio networks; 0.6 micron; 30 MHz; 5 V; CDPD; CMOS IP2M technology; Euclidean algorithms; Reed-Solomon decoder; VLSI implementation; cellular digital packet data communication; clock frequency; complexity; composite field; constant multipliers; die area; low complexity Reed-Solomon encoder; CMOS technology; Clocks; Decoding; Error correction codes; Polynomials; Redundancy; Reed-Solomon codes; System testing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982594

Filename

982594