A multistage amplifier topology with embedded tracking compensation

Author

Ziazadeh, Ramsin M. ; Ng, Hiok-Tiaq ; Allstot, David J.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

361

Lastpage

364

Abstract

A new multistage operational amplifier topology requires only n-2 embedded compensation networks for n gain stages. The passive compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power tracking RC compensation technique assures stability and fast settling over process, voltage, and temperature (PVT) variations. In 0.6 μm n-well CMOS with 5 pF loads, a single-ended 3-stage prototype dissipates 4.2 mW at 3.0 V with 82 dB gain, 230 MHz bandwidth, and 150 V/μs slew rate, and a fully-differential 3-stage design dissipates 11 mW at 2.5 V with 122 dB gain, 138 MHz bandwidth, and 360 V/μs slew rate

Keywords

CMOS analogue integrated circuits; compensation; differential amplifiers; network topology; operational amplifiers; tracking; 0.6 micron; 11 mW; 122 dB; 138 MHz; 2.5 V; 230 MHz; 3.0 V; 4.2 mW; 5 pF; 82 dB; compensation networks; embedded tracking compensation; fully-differential three-stage design; multistage amplifier topology; n-well CMOS; operational amplifier topology; passive compensation circuits; power efficiency; single-ended three-stage prototype; slewing; Bandwidth; Broadband amplifiers; Capacitors; Digital integrated circuits; Frequency; Parasitic capacitance; Poles and zeros; Topology; Transfer functions; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694999

Filename

694999