DocumentCode
2227507
Title
Design of mixed-signal circuit for testability
Author
Jianhua, Feng ; Yihe, Sun ; Shuguo, Li
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear
2001
fDate
2001
Firstpage
616
Lastpage
619
Abstract
The test and design for testability methods for each type of block exist but assume a direct access to the block under test. Thus, an additional design for testability structure using boundary scan and mixed-signal test bus is incorporated for effective test application. With this design, separate specialized tests are applied to analog and digital parts, as well as to interconnects. The area overhead of the test access structure is generally small as it is shown to be inversely proportional to the square root of the block area. While the partitioned architecture provides a reasonable test solution, weakness remains in the test of block interfaces. Delay tests and current measurement tests may provide possible solutions. The problem of testing for systems that use both types of signals is addressed in this paper
Keywords
automatic testing; boundary scan testing; delays; design for testability; integrated circuit measurement; integrated circuit testing; mixed analogue-digital integrated circuits; area overhead; block interfaces; block under test; boundary scan; current measurement tests; delay tests; mixed-signal circuit; mixed-signal test bus; partitioned architecture; specialized tests; test access structure; testability; Circuit faults; Circuit testing; Design for testability; Digital circuits; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit testing; Logic circuits; Logic testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982639
Filename
982639
Link To Document