DocumentCode
2229163
Title
Performance evaluation of a microprocessor with on-chip DRAM and high bandwidth internal bus
Author
Iwata, Shunichi ; Shimizu, Toru ; Korematu, Jiro ; Dosaka, Katsumi ; Tsubota, Hideo ; Saitoh, Kazunori
Author_Institution
Mitsubishi Electr. Corp., Itami, Japan
fYear
1996
fDate
5-8 May 1996
Firstpage
269
Lastpage
272
Abstract
The M32R/D is a 32-bit microprocessor with on-chip 2M-byte (16M-bit) DRAM. It has a 32-bit RISC CPU, 32-bit×16-bit multiply and accumulator, 2M-byte DRAM, 2K-byte cache memory, and a memory controller. The CPU, DRAM, and cache memory are connected with a 128-bit 66.6MHz internal bus. This wide internal bus allows high speed transfer of instructions. The use of a 128-bit bus resulted in a 13% improvement in performance as compared with 32-bit bus
Keywords
microprocessor chips; performance evaluation; reduced instruction set computing; 16 Mbit; 2 Kbyte; 32 bit; 66.6 MHz; M32R/D; RISC CPU; cache memory; high bandwidth internal bus; microprocessor; onchip DRAM; performance evaluation; Application specific integrated circuits; Bandwidth; Cache memory; Central Processing Unit; Control systems; Costs; Energy consumption; Microprocessors; Random access memory; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Conference_Location
San Diego, CA
Print_ISBN
0-7803-3117-6
Type
conf
DOI
10.1109/CICC.1996.511089
Filename
511089
Link To Document