A high-throughput low-cost AES cipher chip

Author

Lin, Tsung-Fu ; Su, Chih-Pin ; Huang, Chih-Tsun ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

85

Lastpage

88

Abstract

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

Keywords

CMOS integrated circuits; clocks; cryptography; design for testability; integrated circuit design; integrated circuit testing; pipeline processing; telecommunication security; 0.35 micron; 1.736 Gbit/s; 128 bit; 192 bit; 2.008 Gbit/s; 2.381 Gbit/s; 200 MHz; 256 bit; AES cipher chip; AES design; Advanced Encryption Standard algorithm; CMOS technology; S-box hardware overhead; basis transformation technique; clock frequency; design testability; hardware cost; hardware implementation; key expansion capability; pipelined design; table-lookup technique; throughput rate; Application specific integrated circuits; CMOS technology; Clocks; Communication system security; Costs; Elliptic curve cryptography; Hardware; Internet; Laboratories; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031538

Filename

1031538