• DocumentCode
    2233559
  • Title

    A low power CMOS adaptive line equalizer for fast Ethernet

  • Author

    Yoo, Kwisung ; Lee, Hoon ; Han, Gunhee

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    129
  • Lastpage
    132
  • Abstract
    An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 μm CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm2).
  • Keywords
    CMOS analogue integrated circuits; LAN interconnection; adaptive equalisers; circuit CAD; circuit simulation; data communication equipment; integrated circuit design; integrated circuit modelling; local area networks; low-power electronics; twisted pair cables; 0.35 micron; 100 m; 155 Mbit/s; 19 mW; CMOS process design; Ethernet data communication bit rate; UTP cable length; equalizer low power consumption; equalizer silicon die area; fast Ethernet low power CMOS analog adaptive line equalizer; unshielded twisted pair cable; Adaptive equalizers; Bandwidth; Circuits; Communication cables; Data communication; Ethernet networks; Filters; Frequency; Poles and zeros; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
  • Print_ISBN
    0-7803-7363-4
  • Type

    conf

  • DOI
    10.1109/APASIC.2002.1031549
  • Filename
    1031549
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2233559