An Design of the 16-Order FIR Digital Filter Based on FPGA

Author

Lin Jieshan ; Huang Shizhen

Author_Institution

Fujian Key Lab. of Microelectron. & Integrated Circuits, Fuzhou Univ., Fuzhou, China

fYear

2009

fDate

26-28 Dec. 2009

Firstpage

489

Lastpage

492

Abstract

At first, this paper analyzes the basic structure and hardware characteristics of the FIR digital filter, and then a design method of the FIR filter is discussed on the basis of the FIR filter structure. It is a method that is based on FPGA, draws the coefficient by Matlab and adopts the pipeline to implete the FIR digital filter. The article focuses on the introduction of the overall framework of the FIR digital filter adopting the finite-state machine as well as the principle of each module of the design. The design is impleted by use of the Verilog hardware description language and each module is verified and simulated by Quartus 8.0 and Modelsim-Altera.

Keywords

FIR filters; field programmable gate arrays; network synthesis; FIR digital filter; FIR filter structure; FPGA; Matlab; Modelsim-Altera; Quartus 8.0; Verilog hardware description language; finite-state machine; hardware characteristics; Digital filters; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware design languages; IIR filters; Laboratories; Logic devices; Microelectronics; Pipeline processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science and Engineering (ICISE), 2009 1st International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-4909-5

Type

conf

DOI

10.1109/ICISE.2009.243

Filename

5455578