A 64 bit parallel CMOS adder for high performance processors

Author

Xu-guang, Sun ; Zhi-Gang, Mao ; Feng-chang, Lai

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., China

fYear

2002

fDate

2002

Firstpage

205

Lastpage

208

Abstract

A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 μm 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling technique, the new adder architecture achieved good performance. The addition latency is 700 ps, 20% faster than that of the conventional architecture adder. The area of the adder is 0.16 mm², similar to that of the conventional one.

Keywords

CMOS logic circuits; adders; digital arithmetic; digital signal processing chips; microprocessor chips; parallel architectures; 0.25 micron; 2.5 V; 64 bit; 700 ps; DSP processors; FET scaling technique; UMC 1-poly 5-metal CMOS technology; adder architecture; clock-delayed domino logic; clock-delayed dynamic logic; dynamic compound gates; high performance processors; microprocessors; modified Kogge-Stone algorithm; parallel CMOS adder; Adders; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Computer architecture; Delay; Digital signal processing; FETs; Microelectronics;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031568

Filename

1031568