Low cost floating point arithmetic unit design

In this paper, we present the FP-AU (Floating Point Arithmetic Unit) that improves the performance of multimedia processing with low hardware cost. The hardware cost was minimized by designing a 32-bit single precision architecture that can execute 64-bit double precision operations with very low hardware overhead, such as a barrel shifter and control logics. Since the FP-AU occupies a significant amount of silicon area in a microprocessor due to double precision data, our proposed architecture shows a very efficient performance/cost ratio. The sticky bit generation logic offers a simple architecture that can reduce hardware cost. The FP-AU was modeled in Verilog HDL and synthesized with 0.35 μm standard cell libraries after verification. The occupied area is about 6,590 equivalent gates. It operates at 130 MHz clock speed under worst-case conditions.