An all-digital PLL clock multiplier

Author

Olsson, Thomas ; Nilsson, Peter

Author_Institution

Dept. of Electroscience, Lund Univ., Sweden

fYear

2002

fDate

2002

Firstpage

275

Lastpage

278

Abstract

A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm². In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system process change simulation.

Keywords

CMOS digital integrated circuits; circuit CAD; clocks; digital phase locked loops; hardware description languages; industrial property; integrated circuit design; integrated circuit measurement; integrated circuit modelling; logic CAD; logic simulation; multiplying circuits; 0.35 micron; 152 to 366 MHz; 3.0 V; CMOS all-digital PLL clock multipliers; CMOS process; PLL frequency range; PLL on-chip area; PLL supply voltage; clock multiplying circuits; digital standard cell libraries; digital system process change simulation; integrated digital PLL; off-chip components; process portable IP-blocks; synthesizable VHDL code; Clocks; Counting circuits; Delay; Detectors; Digital control; Filters; Frequency; Phase locked loops; Ring oscillators; Software libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031585

Filename

1031585