• DocumentCode
    2234418
  • Title

    Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis

  • Author

    Iyer, Balakrishnan ; Karri, Rannesh

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • fYear
    1996
  • fDate
    3-7 Jun, 1996
  • Firstpage
    137
  • Lastpage
    142
  • Abstract
    Introspection, a zero-overhead binding technique during self-diagnosing microarchitecture synthesis is presented. Given a scheduled control data flow graph (CDFG) introspective binding exploits the spare computation and data transfer capacity in a synergistic fashion to achieve low latency fault diagnostics with near zero area overheads without compromising the performance. The resulting on-chip fault latencies are one ten-thousandth (10-4) of previously reported system level diagnostic techniques. A novel feature of the proposed technique is the use of spare data transfer capacity in the interconnect network for diagnostics
  • Keywords
    high level synthesis; logic CAD; microprocessor chips; Introspection; interconnect network; low overhead binding; microarchitecture synthesis; on-chip fault latencies; self-diagnosing; self-diagnosing microarchitecture synthesis; Data flow computing; Delay; Fault detection; Fault diagnosis; Hardware; High level synthesis; Microarchitecture; Permission; Processor scheduling; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference Proceedings 1996, 33rd
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0738-100X
  • Print_ISBN
    0-7803-3294-6
  • Type

    conf

  • DOI
    10.1109/DAC.1996.545560
  • Filename
    545560