A sub-word parallel digital signal processor for wireless communication systems

Author

Yuan-Hao Huang ; Chiueh, Tzi-Dar

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2002

fDate

2002

Firstpage

287

Lastpage

290

Abstract

In this paper, we propose a programmable fixed-point digital signal processor for wireless communications. The architecture of the processor is designed according to the computation requirements of modern communication systems. A decimation-in-frequency (DIF) butterfly unit is built in the processor to enhance the processing capability of FFT operations needed in orthogonal-frequency-division-multiplexing (OFDM) systems. In addition, the butterfly unit can be reconfigured to accelerate squared-difference and add-compare-select calculation in the Viterbi algorithms. A new subword parallel complex-valued multiply-and-accumulate (MAC) architecture is proposed to execute complex/real and single/double precision operations, making it suitable for different requirements of signal formats in signal processing for communication transceivers.

Keywords

CMOS digital integrated circuits; OFDM modulation; Viterbi decoding; digital signal processing chips; fast Fourier transforms; fixed point arithmetic; high-speed integrated circuits; parallel architectures; performance evaluation; programmable circuits; radiocommunication; telecommunication computing; transceivers; 0.35 micron; 3.3 V; 644 mW; 68 MHz; CMOS DSP chip; CMOS digital signal processor; CMOS process; FFT operations; OFDM systems; Viterbi algorithms; add-compare-select calculation acceleration; butterfly unit reconfiguration; communication transceivers; complex-valued MAC architecture; complex/real operations; decimation-in-frequency butterfly unit; multiply-and-accumulate architecture; orthogonal FDM systems; orthogonal frequency division multiplexing; programmable fixed-point DSP; signal formats; signal processing; single/double precision operations; squared-difference calculation acceleration; sub-word parallel DSP; subword parallel MAC architecture; wireless communication systems; Acceleration; Computer architecture; Digital signal processors; OFDM; Process design; Signal processing; Signal processing algorithms; Transceivers; Viterbi algorithm; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031588

Filename

1031588