• DocumentCode
    2234903
  • Title

    Pattern-Based Systematic Task Mapping for Many-Core Processors

  • Author

    Sano, Shintaro ; Sano, Masahiro ; Sato, Shimpei ; Miyoshi, Takefumi ; Kise, Kenji

  • Author_Institution
    Grad. Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Tokyo, Japan
  • fYear
    2010
  • fDate
    17-19 Nov. 2010
  • Firstpage
    173
  • Lastpage
    178
  • Abstract
    The Network-on-Chip (NoC) is a promising interconnection for many-core processors. On the NoC-based many core processors, the network performance of multi-thread programs depends on the method of task mapping. In this paper, we propose a pattern-based task mapping method in order to improve the performance of many-core processors. Evaluation of the proposed method using a detailed software simulator reveals an average performance improvement of at least 4.4%, as compared with standard task mapping using NAS parallel benchmarks.
  • Keywords
    digital simulation; electronic engineering computing; multiprocessing systems; multiprocessor interconnection networks; network-on-chip; NoC; many core processor; multithread program; network-on-chip; processor interconnection; software simulation; systematic task mapping; Network on Chip; many-core processor; task mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networking and Computing (ICNC), 2010 First International Conference on
  • Conference_Location
    Higashi-Hiroshima
  • Print_ISBN
    978-1-4244-8918-3
  • Electronic_ISBN
    978-0-7695-4277-5
  • Type

    conf

  • DOI
    10.1109/IC-NC.2010.33
  • Filename
    5695230
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2234903