Multi-clock domain synchronizers

Modern digital systems become more complex with increasing multi-clocking techniques for better performance. Multiple asynchronous clock domains have been using for different I/O interface in today´s modern system on chip (SoC). Each system needs to communicate with one or other system/peripherals continuously. These multiple asynchronous clock domains are facing meta-stability, data losses and other clock domain crossing (CDC) issues. CDC is an important issue in all today´s SoC. In this paper we have demonstrated how meta-stability occurs in CDC boundary, and presented a comparison of basic synchronizers on the basis of latency time to reduce the propagation of meta-stability, to increase the mean time between failures (MTBF) and to avoid data losses in multi-clock domains.