RTL-TLM equivalence checking based on simulation

The always increasing complexity of digital systems is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels above RTL. The bottom-up approach is often adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models. In this paper, we propose a methodology based on simulation which gives two important contributes. Firstly, it relies on a suite of tools to automate as much as possible the equivalence verification process. Then, a more accurate definition of the equivalence concept is proposed by giving two quality measures of stimuli automatically generated for checking the equivalence between the generated TLM and the RTL golden model.