FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters

This paper describes a reconfigurable hardware implementation for wideband fractional delay FIR filters. The proposed implementation is based on a multirate Farrow structure, reducing in this way the arithmetic complexity compared to the modified Farrow structure, and allowing on line fractional delay value update. A minimax frequency optimization technique is used for computing the structure coefficients. In order to reduce the resources usage the structure filters multiplications are implemented using distribute arithmetic technique. The resulting filter implementation is tested through software simulation and hardware implementation tools. The filter performance is measured in terms of area, throughput and dynamic power consumption. Accordingly to the obtained results the described structure allows the implementation of wideband fractional delay FIR filters with online factional value update. A fine fractional delay resolution is achieved with the proposed hardware implementation.