Improving Source-Follower Buffer for High-Speed ADC Testing

Author

Fan, X.P. ; Chan, P.K.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

21

Lastpage

24

Abstract

An improved CMOS buffer for high-speed ADC testing is presented. It is based on the circuit means to stabilize the DC output voltage of source-follower test buffer through the replica circuit and amplifier in a feedback loop to generate a regulated biasing voltage. With this biasing arrangement, the proposed test buffer maintains high-speed characteristics whilst yet preserving the headroom for test input signal and providing a defined DC output with immunity to variations of process, supply and temperature. In addition, the third-order harmonic distortion of the buffer is analyzed based on a large signal simplified BSIM3 model. The HSPICE simulation results validate the proposed work and correlate well with the distortion analysis on the basis of a standard 0.35 mum CMOS process at a single 3V supply

Keywords

CMOS integrated circuits; analogue-digital conversion; buffer circuits; circuit simulation; 0.35 micron; 3 V; CMOS buffer; CMOS process; DC output voltage stabilization; HSPICE simulation; high-speed ADC testing; large signal BSIM3 model; regulated biasing voltage; source-follower test buffer; third-order harmonic distortion; Circuit testing; DC generators; Feedback circuits; Feedback loop; Harmonic analysis; Harmonic distortion; Signal analysis; Signal processing; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342253

Filename

4145322