High Power CMOS Power Amplifier for WCDMA

Author

Huang, Yu-Chun ; Lin, Zhi-Ming

Author_Institution

Dept. of Electr. Eng., Nat. Changhua Univ. of Educ.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

199

Lastpage

202

Abstract

In this paper we propose a power amplifier (PA) for high output power and high linearity WCDMA applications. This PA is designed based on a three-stage configuration and an output stage designed by a multiple gated transistor topology. The test chip is simulated and fabricated with the TSMC 0.18mum CMOS process. Simulation results show that the power amplifier achieves 24.4 dB of power gain, 25 dBm of 1dB compression power output, and 27.6 dBm at third order output interception point (OIP3). The power added efficiency (PAE) at gain compression point is 33.5%. The die size is 1.2 times 1.2 mm²

Keywords

CMOS analogue integrated circuits; code division multiple access; network topology; power amplifiers; 0.18 micron; 24.4 dB; CMOS power amplifier; CMOS process; WCDMA; gain compression point; multiple gated transistor topology; power added efficiency; three-stage configuration; Driver circuits; Frequency; High power amplifiers; Linearity; Multiaccess communication; Power amplifiers; Power generation; Radiofrequency amplifiers; Topology; Voltage; CMOS; WCDMA; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342366

Filename

4145365