An AWE technique for fast printed circuit board delays

We present a technique for rapidly calculating printed circuit board (PCB) interconnect delays. Because of ringing, plateaux, and other signal integrity effects, delay estimation with low order macromodels is more difficult for PCB nets than for VLSI interconnect. A moment matching method for interconnect trees is described in which moments are computed by a tree traversal algorithm using ABCD matrices. Moment contributions from distributed transmission lines are calculated directly. This is a simplification compared to methods which must first approximate the line as a lumped RLC ladder; it also makes time of flight extraction trivial. Order descent is used to ensure stability. When applied to a real PCB design, the method was accurate and impressively fast-588 nets, or 4496 delays, in 12 seconds on a PC