RC-interconnect macromodels for timing simulation

Most timing simulators obtain their efficiency over circuit simulation in terms of explicit integration algorithms that have difficulty handling the stiff RC circuit models which characterize interconnect-dominated paths. We describe a reduced-order N-port interconnect macromodel for timing simulation. This macromodel is shown to improve the timing simulation efficiency dramatically since it alleviates the stiff circuit problem. Moreover through its compatibility with the simple timing simulation transistor models, it is shown that this macromodel does not suffer from the dramatic increase in complexity with an increase in the number of ports like circuit simulation