DocumentCode
2242159
Title
Testing for Transistor Aging
Author
Baba, A. Hakan ; Mitra, Subhasish
Author_Institution
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
fYear
2009
fDate
3-7 May 2009
Firstpage
215
Lastpage
220
Abstract
Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design during system operation. This paper introduces such testing techniques. Results on large designs demonstrate the practicality and effectiveness of presented techniques.
Keywords
active networks; ageing; automatic testing; combinational circuits; delays; integrated circuit design; integrated circuit reliability; transistor circuits; circuit delay degradation; online circuit failure prediction; online self test; transistor aging; Aging; Built-in self-test; Circuit testing; Clocks; Degradation; Delay; Niobium compounds; System testing; Timing; Titanium compounds; Delay tests; Failure prediction; Transistor aging; path selection; test pattern generation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location
Santa Cruz, CA
ISSN
1093-0167
Print_ISBN
978-0-7695-3598-2
Type
conf
DOI
10.1109/VTS.2009.56
Filename
5116636
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