Methods for on-chip embedding of path delay test vectors

We propose two methods for embedding on-chip a given set of pairs of test patterns that have been generated by an arbitrary ATPG tool for path delay faults. The first method uses an LFSR with multiplexers. It applies to any set of test patterns and it is experimentally verified to have reasonable hardware overhead. The second method applies to the important special case of single input pattern changes within each pair and is very hardware overhead efficient