Comprehensive defect analysis and testability of current-mode logic circuits

Author

Adham, Saman ; Al-Khalili, Dhamin ; Rozon, Côme ; Raez, D.

Author_Institution

Logic Vision, Ottawa, Ont., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

339

Abstract

This paper presents comprehensive defect analysis of digital CML circuits using detailed defect models at the device level. The circuits are based on Nortel´s BiCMOS technology. A defect model macro has been used to analyze fourteen physical defects for each bipolar transistor and where all defects are being qualified as hard or soft. Defects are activated individually within CML gates which are exhaustively simulated and the responses compared to the response of equivalent gold circuits. Extracted data allow us to obtain both defect and fault coverages, and to generate statistics to assess the effectiveness of a given testing approach. For the CML gates studied, logical testing alone is not adequate as the coverage remained between 33% and 79%. By using combined testing the coverage was increased to 100%

Keywords

VLSI; bipolar logic circuits; current-mode logic; fault diagnosis; high-speed integrated circuits; integrated circuit modelling; integrated circuit testing; logic gates; logic testing; CML gates; Nortel BiCMOS technology; bipolar transistor defects; combined testing; comprehensive defect analysis; current-mode logic circuits; defect model macro; device-level defect models; digital CML circuits; fault classification; fault coverage; high speed VLSI circuits; physical defects; statistics; testability; BiCMOS integrated circuits; Bipolar transistors; Circuit faults; Circuit simulation; Circuit testing; Data mining; Gold; Logic devices; Logic testing; Statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.857099

Filename

857099